In data processing systems with sizable main memory capacity, cache memory is usually employed to achieve an optimum ratio of memory cost versus data access speed. In cache memory systems, data in the main memory is "staged" into a cache memory where it is accessed by the central processing unit. Because the speed of the cache memory is higher than that of the main memory, the time spent by the central processing unit in data access will be reduced. However, because of the higher cost of the cache memory, the storage space provided by the cache memory is usually a small subset of the memory space of the main memory. When the storage space in the cache memory is exhausted, data in a portion of the cache memory will be "destaged" back to the main memory to make room for new data.
In many modern large scale data processing systems such as the AMDAHL System/5890, individual systems can be coupled together into a multiprocessor configuration to improve system processing capability and reliability. In one multiprocessor configuration, the main memory facilities of the individual systems are interconnected so that each processor can, in addition to its own memory facility, access the main memory facilities of the other systems. In such configuration, when the cache data of a processor is destaged, it is important to direct the cache data to the proper main memory facilities. Thus, there exists a need for a method and apparatus of destaging cache data in a system which has multiple main memory facilities, and specifically for a method of directing the cache data to a proper main memory facility during a destaging operation.
Furthermore, to ensure data integrity, there is a need for a method and apparatus to ensure proper destaging of the cache data even in the presence of an error in the identification of a source main memory facility in a destaging operation.